The previous PNP matched pair + LM3900-based antilog generator worked, but had several flaws that needed to be remedied. Among them was that there was no mechanism for adding control voltages algebraically, and the input control voltage was inverted, with respect to the output antilog function. Also, voltage control mechanisms for closing the gap on Vcb ≈ 0V were not possible, which could lead to antilog conformity problems. This was a problem because the input control voltage was ground-referenced, not referenced to the +Vbe seen at the LM3900 inputs. Additionally, in the previous circuit, the antilog scale could not be calibrated (which has to be done in connection with the +3300 ppm/°C tempco thermistor). This issue also interacts with having a control voltage adder, because it commits where the thermistor is allowed to be in the circuit.
All these issues were all addressed with the updated circuit design, which was done in three separate sections, to address specific parts that are related to each other.
The first issue addressed was getting a precise control voltage adder that could accept 0V inputs, and then normalizing the range of control voltage from 18:1, plus inserting the tempo thermistor. Because this system is working with a unipolar supply, and voltage addition requires inversion from op amp negative feedback, the adder has to have a reference voltage to reflect from. As well, this reference voltage needs to be temperature stable, so as to not introduce other temperature dependencies. Temperature stability was done by using a 1N5232B 5.6 Zener diode and one of the op amps in a feedback loop, to form a voltage regulator per AN-72. The temperature coefficient of the diode and +Vbe of the -input in the regulator op amp cancel each other out to a very large degree. The voltage out of the "regulator" (which here is actually used as as reference) was quite stable over various heat soak tests conducted. This reference voltage is then used to set the current into the +input to preset the +Vout of amplifer 3 to +10.00V, when the input signal is 0.00V. This is the "platform" all added control voltages will reflect from. Op amp 3 then has a level-shifting emitter follower, to enable 0V output under load. The load in this case is the 18:1 adjustable voltage attenuator, which enables 1V/octave scaling of 18mv per octave, at what will be one of the bases of the antilog generator transistor pair. This attenuator also includes the tempco thermistor. This part of the circuit is shown in the next engineering notebook page:
Control voltage adder, voltage reference, and signal normalization
After inverting a 0-10V input range into an inverting 10-0V output, then the attenuated signal produces 180mV-0V out, ground-referenced. To normalize this 180mV ΔV to the antilog matched pair transistors which have collectors tied to +Vbe of the LM3900 inputs, a further level shift upward has to be done. This was a little bit complicated. As well, the relative overlap between a fixed base voltage and the variable ΔV needs to occur, so that the 180mV can appear as ±90mV relative to the fixed voltage. Then, both base voltages need to raised or lowered so as to able set the input ΔV at within the active Vbe range of the antilog transistors. Incidentally, the antilog transistors may not have exactly the same Vbe as the LM3900 inputs, so some leeway is needed. The circuit below does these jobs:
Vbe offset and balance amplifiers
Last is the actual antilog generator stage. The transistors need to be turned on, so the emitters need to be biased at ≈+2Vbe to allow +1Vbe ±90mV control one base (the other is held at +1Vbe, constantly), with the collectors simultaneously tied to +1Vbe. A constant current supplied through one side is also needed to allow Is cancellation (another related tempco for antilog circuits), and op amp 1 does this, using a variation of a NVbe multiplier described in AN-72. In the configuration shown, negative feedback forces op amp 1 (from a second LM3900) to push ≈22μA through the transdiode connected transistor at bottom; due to the stack of up voltage drops, this also puts the emitters of the matched pair at ≈+2Vbe, for the 2SA798 dual PNP device. Finally, the readout current is transformed into a level-shifted output voltage via op amp 3 (also from the second LM3900), which replicates the NPN emitter follower as a powered level shifter seen before in the control voltage adder. The last part of the antilog generator is shown in the next page:
Antilog circuit and readout amplifier
I/O transfer function of the Antilog generator
The circuit can and does work! It's also relatively temperature stable, and produces a clean transfer function. The scope foto belows shows a 0-10V input transformed into a ≈0-8V antilogarithmic output calibrated for 1V/octave against the input.
The antilog will always produce a minimum non-zero output, and that's 36mV in the present circuit. The max output could be preset to +10V, but in order to see it on one scope screen that's only 8 divisions tall at 1V/division, an 8V limit was set for the peak output. It appears that the minimum ouput could be lowered further with some additional tweaks in the dual +1Vbe balancing circuit, but the present circuit is useful as-is. Fabricating an evaluation board might be in development, to provide further analysis and some circuit tweaking, in a more hospitable environment than a superstrip breadboard.
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