I've been designing a new kind of envelope generator with the LM3900, for which the recent high-performance integrator work was about. One key design problem with the integrator was obtaining the necessary control range from rotary controls like potentiometers, using them strictly as linear control voltage generators. Basically, it's undesirable to have use a non-linear (such as a D-taper) pot, and I did not want the delay generation to be created directly via resistance in a RC circuit, like with a 1-2MΩ pot. Instead the ADSR controls just need to be a voltage source for other voltage-controlled circuits. In particular so that external control voltages can be used as well as the control setting pots. So: best to have one kind of consistent voltage control mechanism, and one answer is to use an antilog generator to map linear input control voltages to antilog output voltages -- but as we'll see shortly, there is an even better solution.
After building a precision normalized (1V/OCT) LM3900-based antilog generator intended for accurate pitch generation, I returned to the original unnormalized circuit that started the concept, New LM3900 Antilog Generator. These designs all use a single +15V power supply. I had vague recollection of some useful properties, but in particular I knew for the envelope generator that I wanted a single-supply LM3900 antilog solution with less parts count than the precision antilog generator (which I also want to improve, at some time later). So, I took another look at the original circuit. The resulting research notes and more technical information are below.
Research Notes: Updated Single Supply Antilog Generator
This was most fortuitous! Because I made a number of discoveries about how well the original circuit works, and also how well-suited it is for the envelope control generation solution. Details on this follow.
First, the normalization "defect" of the original circuit is a total win for voltage-to-time applications. Extra LM3900 circuitry was needed in the precision circuit to translate a positive 0-10V control voltage range into a ∆V=180mV of the correct polarity and also uplifted 1Vbe above ground to control the base of one of the differential pair transistors.
Update October 16, 2022: from later research, it appears that the reciprocal V/OCT effect is reversible (e.g. can also go to normal V/OCT). This depends on what ∆Vbe offset is used at the base of Q1 with the input DC attenuator circuit, relative to the fixed +1Vbe transistor Q2. A subsequent circuit build of the above design as-drawn shows the normal V/OCT response: it merely had a different ∆Vbe offset. A positive ramp of 0-10V is inverted as a 180mV negative ramp set as ±90mV about +1Vbe. This causes an exponentially increasing current in the antilog transistor Q2. This is also the same mechanism by which the circuit can be programed to work with negative input voltages.
In the original or first of these simpler antilog circuits, the I/O characteristic is a reciprocal: a low control voltage (0V) causes maximum antilog voltage out, and a high control voltage (10V) causes a low antilog voltage out. This is absolutely perfect for voltage-to-time generation. For an ADSR, a timing control knob at maximum left produces 0V, and this results in the fastest time rate. As the control is moved right to the full extent, slower and slower time rates are produced. The reciprocal antilog I/O characteristic also allows the proportion of rotary change on the knobs to be non-linear, so that time rates are not bunched together, as controls are moved clockwise from left-to-right. Perfect!
Secondly, in re-investigating the original concept circuit design, I wanted to test using the more commonly available high-β 2N5087 PNP transistors, and not apply the harder-to-get 2SA798 matched PNP pair. I've already had good luck in transistor circuit design with the 2N5087 devices. The devices were selected at random and while not tested for matching, they are close enough in characteristics so as to work extremely well for antilog conformity.
But there's more, as this circuit has other almost magical properties. A quick description of operation is needed to introduce these other properties.
The circuit basically sets up a differential PNP pair as the antilog transistors, where a linear ∆Vbe results in an antilog Ic. Op amp 4 sets the Q2 baseline at +1Vbe, while op amp 1 via one of the transistors, creates an emitter voltage across the pair notionally at +2Vbe, but at a constant current, which causes the emitter line to shift linearly to accommodate the ∆Vbe introduced by op amp 3. Op amp 3 has LM3900 common mode biasing to allow input voltages down to 0 volts, or even lower, to -10V or more. The -input and feedback resistors on op amp 3 act to reduce a 10V signal range down to 180mV, which at 25℃ represents ±5 octaves of Ic from the antilog transistor Q2. The +input to op amp 3 uses a resistor and trimmer with the +15V supply as a reference to DC align the 180mV signal to approximately ±90mV onto base of Q1. This alignment is relative to the baseline at Q2, the antilog readout transistor. The 1MΩ trimmer provides sufficient adjustment range that the input control voltage can be set 0 to +10V, or even to -10V to 0V. Depending on the range, this trimmer effectively calibrates the peak antilog Vo for the smallest input control voltage. As shown in the scope fotos, up to +14V range is available from this circuit, some 40% overrange for a +10V circuit. The +input to op amp 2 directly senses the readout transistor Ic, producing a positive voltage out via current mirror action into the 15.0K 1% feedback resistor at the -input.
A somewhat hard to see thing in the circuit as-drawn is that the 22pF roll off capacitor around op amp 1 is now the only feedback; this op amp is not only an integrator with a 22pF capacitor. In fact the larger feedback loop for op amp is via Q1, and it's for DC control, to setup a +2Vbe voltage level at the Q1/Q2 emitters, while maintaining a constant current established by the 59k resistor to ground at the -input of op amp 1. The diode connected transistor plus the diode at the -input establish a +2Vbe output level.
This circuit design is favorable because the collection of cascaded PTAT transistor circuits tend to generally oppose each other. The ∆Vbe stackup within the NPN transistors of the LM3900 +input current mirrors and -inputs to a very good degree equal the opposing ∆Vbe stackup for the PNP differential pair transistors -- the circuit is approximately thermally stable by default.
This was learned by heat testing just the PNP differential pair, then seeing compensating action just heating the LM3900. Thermal impulse does matter, as the differential pair and the LM3900 have differing thermal time constants. The BJTs respond more quickly, whereas the LM3900 responds more slowly. In addition, the LM3900 has more response range (down) than the BJTs do (up), evidently. So there is still some potential drift, because the up/down balancing effects are not completely even, on the breadboard.
This effect may be larger than it should be though. My test breadboard might be much worse than a PCB. I did not create any thermal coupling between the opposing elements (see breadboard foto, below). But presuming the design would be in an operating environment where there would only be a very slow macro thermal gradient (e.g. gradual changes in room temperature) upon an implementation printed circuit board, and that the LM3900 and BJTs could be thermally connected, the basic temperature compensation seems usable. This scenario seems more realistic than thermal pulse testing done on a wide-open breadboard.
What's also interesting about the reciprocal antilog I/O characteristic is that any small residual thermal effect that is not resolved by the integral temperature compensation would also have no perceivable affect on the sound of a voltage-to-time circuit (like an ADSR). This is because the largest residual error is on the fastest slope generated by a voltage-to-time generator. It's not too easy to hear the difference between a 12mS ramp versus a 10mS one when driving a VCA. This particular case presumes as much as 20% error, but the thermal compensation is a good deal better than that. Moreover, for the slower voltage-to-time ramps, as the control voltage climbs up, and the output antilog voltage goes down, any residual error becomes smaller and smaller. There is almost no thermal change in the last several octaves at the lowest end of the antilog output. The arrangement of opposing polarities is such that the LM3900 output at the very lowest output becomes a constant fixed reference voltage under all conditions. This constant "offset voltage" can be calibrated out to zero in the succeeding voltage-to-current integrator stage, affording a very large dynamic range for voltage-to-time waveform generation. The scope fotos below illustrate virtually unchanged conditions for the last few octaves under thermal test, and these impact the precision of the slowest ramps that would be generated in a voltage-to-time circuit. So, when the subsequent voltage-to-time stage is calibrated for (say) a 10 second interval, that calibration is likely to hold true as would that for several successive halvings in time duration.
The circuit worked extremely well even with an uncritical solderless breadboard implementation. Note that the discrete 2N5087 pair aren't even thermally coupled, nor are they thermally connected to the LM3900.
Implementation of Updated Single Supply Antilog Generator
Scope fotos further illustrating the operation of the Antilog Generator:
Calibrated I/O for 0-10V range
Calibration changed to provide maximum unclipped antilog output response ≈14Vpp
0-10V input voltage sweep (ORN) vs. Vbe voltage measurements (Q1B - VIO, Q1E/Q2E - CYAN, Q2B-GRN)
Magnified view of low-voltage antilog output for last several octaves
+20% Vo error heating only the 2N5087 differential pair transistors; heating only the LM3900 itself counter-acts this change! With both under heat flux, close to 0 tempco results: PNP ∆Vbe ≈ NPN ∆Vbe, but with opposite signs.
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